What is Interrupt and Interrupt Cycle?

Interrupt

An interrupt in the 8085 microprocessor is a request to stop program execution and go do something else, such as service a device request or hardware condition. The interrupt return sequence restores normal program flow to where it was interrupted.

Interrupt Cycle

An interrupt cycle is a memory fetch sequence generated in response to the interrupt request. It can be identified in hardware by the status lines, and the expected response is an op-code, optionally followed by immediate bytes, such as the address of a CALL instruction. Except, see interrupt types below.

There are three types of interrupts:

The INTR pin causes a (traditional 8080) hardware interrupt cycle, where the external hardware provides an out-of-band opcode. This is usually an RST instruction or a CALL instruction.

The RST instructions generate a software interrupt that vectors to low memory. There are eight RST instructions, RST 0 through RST 7. The number is multiplied by 8, and that is the address of the next instruction to execute, 0H, 8H, 10H, etc.

The RST5.5, RST6.5, RST7.5, and TRAP pins are hardware interrupts. Unlike the INTR pin, they do not require the hardware to provide an opcode. Instead, they implicitly generate the equivalent of an RST instruction. They are named x.5 because they fit in halfway between the traditional RST vectors, i.e. RST6.5 vectors to 34H, in between 30H for RST 6 and 38H for RST 7. TRAP is at 24H.

RST5.5 and RST6.5 are level triggered. They must be cleared before the IE flag is enabled. RST 7.5 is edge triggered, and will not be triggered until the next leading edge. The IE flag must still be re-enabled. TRAP is both edge and level triggered. It sets at leading edge, and must remain asserted until the interrupt sequence starts. It will refire on next edge, and it cannot be disabled.

The interrupt service routine is expected to save and restore the machine state, so that the interrupted program is not disturbed. Except for the delay in processing.