IAP practicals Published

Practicals for subject IAP are published for download on the website:
http://sites.google.com/site/vpmpce/downloads

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Students. . .
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SAD Assignment- 4th SEM

System Analysis and Design

Assignment:1

1. Write a note on software engineering discipline.
2. Differentiate: Programs vs Software Products.
3. Write a note on : Software life cycle models along with its advantages and drawbacks.
4. Describe: Iterative Waterfall Model.
5. Describe: Evolutionary Model.

Assignment: 2

1. Describe: Prototyping Model.
2. Describe: Spiral Model.
3. Explain the ‘feasibility study’ phase of SDLC.
4. Explain ‘System Analysis’, ‘System Design’ & ‘Maintenance’ phase of SDLC.
5. What is SDLC? Note down the phases of SDLC & also Draw the diagram that explains the working of SDLC.
6. What is Documentation? Explain in brief: Uses, Principles & Types of Documentation.

Assignment:3

1. Write a note on: Requirement Gathering and Analysis.
2. Describe the contents of an SRS document.
3. Explain the characteristics of a good SRS document.
4. Write a note on: Operational Semantics.
5. State the Merits & Limitations of Formal Methods.
6. What is s formal technique? Explain.

Assignment: 4

1. Explain: Interviews, along with its advantages , Drawbacks and Types.
2. Write a note on: Group Communications & Presentation.
3. Explain: System Design, Process Modelling and logical and physical design.
4. What is a data flow diagram? State the characteristics and rules of a DFD.

COA Assignments- 4th CE

Computer Organisation and Architecture

Assignment - 1

Q. Write down a short-note on following

            1. Register

            2. Decoder

            3. Encoder

            4. Multiplexer

            5. IC

Assignment - 2

Q.1 Write down the definition on following

            1. Digital System

            2. Micro Operation

            3. Register Transfer Language

Q.2 Explain register transfer in using block diagram and time diagram.

Q.3 What is bus? Explain bus transfer with block diagram.

Q.4 Explain three state bus buffers detail with block diagram.

Q.5 Explain memory transfer.

Q.6 What are the basic arithmetic micro-operation? Give the overview.

Q.7 What is a binary adder? Explain 4-bit binary adder with block diagram.

Q.8 Explain binary adder - subtractor with block diagram of 4-bit adder - subtractor.

Q.9 Explain binary incrementer using a block diagram of 4-bit binary incrementer.

Assignment - 3

Q.1 Draw block diagram of arithmetic circuit & explain with using truth table.

Q.2 What are the logic basic micro-operations? Explain in brief with truth table.

Q.3 Explain Application of logic micro-operations in detail.

Q.4 Explain various shift micro-operations.

Q.5 Explain 4-bit combinational circuit – shifter.

Q.6 Explain arithmetic logic shift unit in detail.

Assignment - 4

Q.1 Define the following terms.

            a. Program

            b. Instruction

            c. Instruction code

            d. Operation code

            e. Effective address

Q.2 Explain direct and indirect addressing modes with example.

Q.3 Explain basic computer register with example.

Q.4 Draw the diagram of common bus for register and memory.

Q.5 Explain formats of various types of computer instruction with diagram.

Q.6 Explain control unite of a basic computer.

Q.7 Explain instruction cycle with each phase in detail.

Q.8 Explain interrupt cycle with flowchart.

What is Interrupt and Interrupt Cycle?

Interrupt

An interrupt in the 8085 microprocessor is a request to stop program execution and go do something else, such as service a device request or hardware condition. The interrupt return sequence restores normal program flow to where it was interrupted.

Interrupt Cycle

An interrupt cycle is a memory fetch sequence generated in response to the interrupt request. It can be identified in hardware by the status lines, and the expected response is an op-code, optionally followed by immediate bytes, such as the address of a CALL instruction. Except, see interrupt types below.

There are three types of interrupts:

The INTR pin causes a (traditional 8080) hardware interrupt cycle, where the external hardware provides an out-of-band opcode. This is usually an RST instruction or a CALL instruction.

The RST instructions generate a software interrupt that vectors to low memory. There are eight RST instructions, RST 0 through RST 7. The number is multiplied by 8, and that is the address of the next instruction to execute, 0H, 8H, 10H, etc.

The RST5.5, RST6.5, RST7.5, and TRAP pins are hardware interrupts. Unlike the INTR pin, they do not require the hardware to provide an opcode. Instead, they implicitly generate the equivalent of an RST instruction. They are named x.5 because they fit in halfway between the traditional RST vectors, i.e. RST6.5 vectors to 34H, in between 30H for RST 6 and 38H for RST 7. TRAP is at 24H.

RST5.5 and RST6.5 are level triggered. They must be cleared before the IE flag is enabled. RST 7.5 is edge triggered, and will not be triggered until the next leading edge. The IE flag must still be re-enabled. TRAP is both edge and level triggered. It sets at leading edge, and must remain asserted until the interrupt sequence starts. It will refire on next edge, and it cannot be disabled.

The interrupt service routine is expected to save and restore the machine state, so that the interrupted program is not disturbed. Except for the delay in processing.

Mobile Community for students(cestudents)

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VPMP Polytechnic